present invention relates generally to the testing and clocking of microprocessors that perform bit slicing, and more specifically to a computer circuit and logic function which combines resynchronization stages with part of the clock circuit in order to expedite resynchronization.
Many bit-slice applications require that the clock enters a wait mode (Wait states added) until an asynchronous input occurs (such as transfer acknowledge, FIFO input ready, FIFO output ready, etc). In a single micro-cycle operation, the clock and test circuit must accomplish the following
the clock circuit must decode what kind of operation is to be performed and select the proper test input; PA1 the clock should allow some time for the test input to become stable before testing; PA1 the test input should be cleared (wait states to be added) at the beginning of the cycle to prevent previous test conditions from releasing the clock; and PA1 when the asynchronous input becomes valid, two stages of synchronization should be used before the next micro-cycle clock is generated. PA1 the clock circuit must free run during reset; PA1 some applications might require synchronous wait operations as well as asynchronous; and PA1 some applications might require programmable cycle lengths. PA1 U.S. Pat. No. 3,343,141, issued to Hackl; PA1 U.S. Pat. No. 4,241,416, issued to Tarczy-Hornoch; PA1 U.S. Pat. No. 4,253,183, issued to Taylor et al; PA1 U.S. Pat. No. 4,381,540, issued to Lewis et al; PA1 U.S. Pat. No. 4,418,383, issued to Doyle et al; PA1 U.S. Pat. No. 4,454,589, issued to Miller; and PA1 U.S. Pat. No. 4,528,641, issued to Burrows.
Some additional clocking operations might include:
The task of resynchronizing microprocessors after they receive asynchronous inputs (such as FIFO inputs, transfer, acknowledge, etc.) is alleviated, to some extent, by the systems disclosed in the following U.S. Patents, the disclosures of which are incorporated herein by reference:
The Miller reference discloses a programmable arithmetic logic unit for performing high speed bit sliced computations. A bit slicer is also shown in the Burrows patent.
Doyle et al is included for its references to bit slicing and the patent's discussion of the bit slicing process. Lewis et al disclose an asynchronous device for formulating channel error status information in a data processor.
Tarczy-Hornoch is directed to a microprocrocessor monitor or analyzer useable with all microprocessor families having accessible or reconstructible address and data busses up to 16 bits wide each.
Hackl discloses a system for by-passing the main source of internal gating and sequence selecting control signals of a data processor to permit diagnostic testing. In Taylor et al faults in a data processor are diagnosed in conjunction with the storage of signals at test points in the execute stage of the processor during the execution of a command-under-test.
The conventional resynchronizing approach used in prior art systems is to inhibit the clock partway through its cycle. This inhibit continues until the re-synchronized test input becomes valid. The clock then proceeds to complete its cycle.
The problem with the conventional approach is that after the asynchronous input has arrived, the clock circuit must still wait for the re-synchronization process to occur before it can continue. This means one or two overhead wait states are added after the input becomes valid. This problem of overhead wait states is particularly agonizing when the input becomes valid before the clock ever reaches its inhibit phase. In this case, the clock should be able to proceed without adding any wait states. Unfortunately, the clock will still have to add one (or two) overhead wait states just to allow the input test circuitry enough time to clear the input test and complete the two stages of synchronization.
In view of the foregoing discussion, it is apparent that there currently exists the need for a resynchronizing system that minimizes the overhead wait stages after an asynchronous input has been supplied to a microprocessor. The present invention is intended to satisfy that need.